forked from JeremyStarTM/aur-linux-clear
5.6.13-3 (clr 5.6.13-952) add rebase gcc patch
This commit is contained in:
Josip Ponjavic
parent
a808e9b482
commit
9d51bd9988
1 changed files with 663 additions and 0 deletions
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@ -0,0 +1,663 @@
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WARNING
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This patch works with gcc versions 10.1+ and with kernel versions <5.7 and should
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NOT be applied when compiling on older versions of gcc due to key name changes
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of the march flags introduced with the version 4.9 release of gcc.[1]
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Use the older version of this patch hosted on the same github for older
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versions of gcc.
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FEATURES
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This patch adds additional CPU options to the Linux kernel accessible under:
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Processor type and features --->
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Processor family --->
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The expanded microarchitectures include:
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* AMD Improved K8-family
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* AMD K10-family
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* AMD Family 10h (Barcelona)
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* AMD Family 14h (Bobcat)
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* AMD Family 16h (Jaguar)
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* AMD Family 15h (Bulldozer)
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* AMD Family 15h (Piledriver)
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* AMD Family 15h (Steamroller)
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* AMD Family 15h (Excavator)
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* AMD Family 17h (Zen)
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* AMD Family 17h (Zen 2)
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* Intel Silvermont low-power processors
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* Intel Goldmont low-power processors (Apollo Lake and Denverton)
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* Intel Goldmont Plus low-power processors (Gemini Lake)
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* Intel 1st Gen Core i3/i5/i7 (Nehalem)
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* Intel 1.5 Gen Core i3/i5/i7 (Westmere)
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* Intel 2nd Gen Core i3/i5/i7 (Sandybridge)
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* Intel 3rd Gen Core i3/i5/i7 (Ivybridge)
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* Intel 4th Gen Core i3/i5/i7 (Haswell)
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* Intel 5th Gen Core i3/i5/i7 (Broadwell)
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* Intel 6th Gen Core i3/i5/i7 (Skylake)
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* Intel 6th Gen Core i7/i9 (Skylake X)
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* Intel 8th Gen Core i3/i5/i7 (Cannon Lake)
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* Intel 10th Gen Core i7/i9 (Ice Lake)
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* Intel Xeon (Cascade Lake)
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* Intel Xeon (Cooper Lake)
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* Intel 3rd Gen 10nm++ i3/i5/i7/i9-family (Tiger Lake)
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It also offers to compile passing the 'native' option which, "selects the CPU
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to generate code for at compilation time by determining the processor type of
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the compiling machine. Using -march=native enables all instruction subsets
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supported by the local machine and will produce code optimized for the local
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machine under the constraints of the selected instruction set."[3]
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MINOR NOTES
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This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9
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changes. Note that upstream is using the deprecated 'match=atom' flags when I
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believe it should use the newer 'march=bonnell' flag for atom processors.[2]
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It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The
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recommendation is to use the 'atom' option instead.
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BENEFITS
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Small but real speed increases are measurable using a make endpoint comparing
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a generic kernel to one built with one of the respective microarchs.
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See the following experimental evidence supporting this statement:
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https://github.com/graysky2/kernel_gcc_patch
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REQUIREMENTS
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linux version <=5.6
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gcc version >=10.1
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ACKNOWLEDGMENTS
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This patch builds on the seminal work by Jeroen.[5]
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REFERENCES
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1. https://gcc.gnu.org/gcc-4.9/changes.html
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2. https://bugzilla.kernel.org/show_bug.cgi?id=77461
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3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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4. https://github.com/graysky2/kernel_gcc_patch/issues/15
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5. http://www.linuxforge.net/docs/linux/linux-gcc.php
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--- a/arch/x86/include/asm/module.h 2020-05-14 01:58:30.000000000 -0400
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+++ b/arch/x86/include/asm/module.h 2020-05-16 10:10:41.903122145 -0400
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@@ -25,6 +25,40 @@ struct mod_arch_specific {
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#define MODULE_PROC_FAMILY "586MMX "
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#elif defined CONFIG_MCORE2
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#define MODULE_PROC_FAMILY "CORE2 "
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+#elif defined CONFIG_MNATIVE
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+#define MODULE_PROC_FAMILY "NATIVE "
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+#elif defined CONFIG_MNEHALEM
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+#define MODULE_PROC_FAMILY "NEHALEM "
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+#elif defined CONFIG_MWESTMERE
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+#define MODULE_PROC_FAMILY "WESTMERE "
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+#elif defined CONFIG_MSILVERMONT
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+#define MODULE_PROC_FAMILY "SILVERMONT "
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+#elif defined CONFIG_MGOLDMONT
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+#define MODULE_PROC_FAMILY "GOLDMONT "
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+#elif defined CONFIG_MGOLDMONTPLUS
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+#define MODULE_PROC_FAMILY "GOLDMONTPLUS "
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+#elif defined CONFIG_MSANDYBRIDGE
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+#define MODULE_PROC_FAMILY "SANDYBRIDGE "
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+#elif defined CONFIG_MIVYBRIDGE
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+#define MODULE_PROC_FAMILY "IVYBRIDGE "
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+#elif defined CONFIG_MHASWELL
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+#define MODULE_PROC_FAMILY "HASWELL "
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+#elif defined CONFIG_MBROADWELL
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+#define MODULE_PROC_FAMILY "BROADWELL "
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+#elif defined CONFIG_MSKYLAKE
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+#define MODULE_PROC_FAMILY "SKYLAKE "
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+#elif defined CONFIG_MSKYLAKEX
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+#define MODULE_PROC_FAMILY "SKYLAKEX "
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+#elif defined CONFIG_MCANNONLAKE
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+#define MODULE_PROC_FAMILY "CANNONLAKE "
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+#elif defined CONFIG_MICELAKE
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+#define MODULE_PROC_FAMILY "ICELAKE "
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+#elif defined CONFIG_MCASCADELAKE
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+#define MODULE_PROC_FAMILY "CASCADELAKE "
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+#elif defined CONFIG_MCOOPERLAKE
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+#define MODULE_PROC_FAMILY "COOPERLAKE "
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+#elif defined CONFIG_MTIGERLAKE
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+#define MODULE_PROC_FAMILY "TIGERLAKE "
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#elif defined CONFIG_MATOM
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#define MODULE_PROC_FAMILY "ATOM "
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#elif defined CONFIG_M686
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@@ -43,6 +77,28 @@ struct mod_arch_specific {
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#define MODULE_PROC_FAMILY "K7 "
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#elif defined CONFIG_MK8
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#define MODULE_PROC_FAMILY "K8 "
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+#elif defined CONFIG_MK8SSE3
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+#define MODULE_PROC_FAMILY "K8SSE3 "
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+#elif defined CONFIG_MK10
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+#define MODULE_PROC_FAMILY "K10 "
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+#elif defined CONFIG_MBARCELONA
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+#define MODULE_PROC_FAMILY "BARCELONA "
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+#elif defined CONFIG_MBOBCAT
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+#define MODULE_PROC_FAMILY "BOBCAT "
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+#elif defined CONFIG_MBULLDOZER
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+#define MODULE_PROC_FAMILY "BULLDOZER "
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+#elif defined CONFIG_MPILEDRIVER
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+#define MODULE_PROC_FAMILY "PILEDRIVER "
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+#elif defined CONFIG_MSTEAMROLLER
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+#define MODULE_PROC_FAMILY "STEAMROLLER "
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+#elif defined CONFIG_MJAGUAR
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+#define MODULE_PROC_FAMILY "JAGUAR "
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+#elif defined CONFIG_MEXCAVATOR
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+#define MODULE_PROC_FAMILY "EXCAVATOR "
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+#elif defined CONFIG_MZEN
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+#define MODULE_PROC_FAMILY "ZEN "
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+#elif defined CONFIG_MZEN2
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+#define MODULE_PROC_FAMILY "ZEN2 "
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#elif defined CONFIG_MELAN
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#define MODULE_PROC_FAMILY "ELAN "
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#elif defined CONFIG_MCRUSOE
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--- a/arch/x86/Kconfig.cpu 2020-05-14 01:58:30.000000000 -0400
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+++ b/arch/x86/Kconfig.cpu 2020-05-16 10:12:29.508752718 -0400
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@@ -116,6 +116,7 @@ config MPENTIUMM
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config MPENTIUM4
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bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
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depends on X86_32
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+ select X86_P6_NOP
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---help---
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Select this for Intel Pentium 4 chips. This includes the
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Pentium 4, Pentium D, P4-based Celeron and Xeon, and
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@@ -148,9 +149,8 @@ config MPENTIUM4
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-Paxville
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-Dempsey
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-
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config MK6
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- bool "K6/K6-II/K6-III"
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+ bool "AMD K6/K6-II/K6-III"
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depends on X86_32
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---help---
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Select this for an AMD K6-family processor. Enables use of
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@@ -158,7 +158,7 @@ config MK6
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flags to GCC.
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config MK7
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- bool "Athlon/Duron/K7"
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+ bool "AMD Athlon/Duron/K7"
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depends on X86_32
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---help---
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Select this for an AMD Athlon K7-family processor. Enables use of
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@@ -166,12 +166,90 @@ config MK7
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flags to GCC.
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config MK8
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- bool "Opteron/Athlon64/Hammer/K8"
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+ bool "AMD Opteron/Athlon64/Hammer/K8"
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---help---
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Select this for an AMD Opteron or Athlon64 Hammer-family processor.
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Enables use of some extended instructions, and passes appropriate
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optimization flags to GCC.
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+config MK8SSE3
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+ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
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+ ---help---
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+ Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
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+ Enables use of some extended instructions, and passes appropriate
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+ optimization flags to GCC.
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+
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+config MK10
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+ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
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+ ---help---
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+ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
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+ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
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+ Enables use of some extended instructions, and passes appropriate
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+ optimization flags to GCC.
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+
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+config MBARCELONA
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+ bool "AMD Barcelona"
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+ ---help---
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+ Select this for AMD Family 10h Barcelona processors.
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+
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+ Enables -march=barcelona
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+
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+config MBOBCAT
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+ bool "AMD Bobcat"
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+ ---help---
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+ Select this for AMD Family 14h Bobcat processors.
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+
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+ Enables -march=btver1
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+
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+config MJAGUAR
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+ bool "AMD Jaguar"
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+ ---help---
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+ Select this for AMD Family 16h Jaguar processors.
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+
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+ Enables -march=btver2
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+
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+config MBULLDOZER
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+ bool "AMD Bulldozer"
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+ ---help---
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+ Select this for AMD Family 15h Bulldozer processors.
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+
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+ Enables -march=bdver1
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+
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+config MPILEDRIVER
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+ bool "AMD Piledriver"
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+ ---help---
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+ Select this for AMD Family 15h Piledriver processors.
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+
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+ Enables -march=bdver2
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+
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+config MSTEAMROLLER
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+ bool "AMD Steamroller"
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+ ---help---
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+ Select this for AMD Family 15h Steamroller processors.
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+
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+ Enables -march=bdver3
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+
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+config MEXCAVATOR
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+ bool "AMD Excavator"
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+ ---help---
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+ Select this for AMD Family 15h Excavator processors.
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+
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+ Enables -march=bdver4
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+
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+config MZEN
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+ bool "AMD Zen"
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+ ---help---
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+ Select this for AMD Family 17h Zen processors.
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+
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+ Enables -march=znver1
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+
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+config MZEN2
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+ bool "AMD Zen 2"
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+ ---help---
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+ Select this for AMD Family 17h Zen 2 processors.
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+
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+ Enables -march=znver2
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+
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config MCRUSOE
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bool "Crusoe"
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depends on X86_32
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@@ -253,6 +331,7 @@ config MVIAC7
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config MPSC
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bool "Intel P4 / older Netburst based Xeon"
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+ select X86_P6_NOP
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depends on X86_64
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---help---
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Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
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@@ -262,8 +341,19 @@ config MPSC
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using the cpu family field
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in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
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+config MATOM
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+ bool "Intel Atom"
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+ select X86_P6_NOP
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+ ---help---
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+
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+ Select this for the Intel Atom platform. Intel Atom CPUs have an
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+ in-order pipelining architecture and thus can benefit from
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+ accordingly optimized code. Use a recent GCC with specific Atom
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+ support in order to fully benefit from selecting this option.
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+
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config MCORE2
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- bool "Core 2/newer Xeon"
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+ bool "Intel Core 2"
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+ select X86_P6_NOP
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---help---
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Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
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@@ -271,14 +361,151 @@ config MCORE2
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family in /proc/cpuinfo. Newer ones have 6 and older ones 15
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(not a typo)
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-config MATOM
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- bool "Intel Atom"
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+ Enables -march=core2
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+
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+config MNEHALEM
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+ bool "Intel Nehalem"
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+ select X86_P6_NOP
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---help---
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- Select this for the Intel Atom platform. Intel Atom CPUs have an
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- in-order pipelining architecture and thus can benefit from
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- accordingly optimized code. Use a recent GCC with specific Atom
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- support in order to fully benefit from selecting this option.
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+ Select this for 1st Gen Core processors in the Nehalem family.
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+
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+ Enables -march=nehalem
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+
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+config MWESTMERE
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+ bool "Intel Westmere"
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+ select X86_P6_NOP
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+ ---help---
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+
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+ Select this for the Intel Westmere formerly Nehalem-C family.
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+
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+ Enables -march=westmere
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+
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+config MSILVERMONT
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+ bool "Intel Silvermont"
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+ select X86_P6_NOP
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+ ---help---
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+
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+ Select this for the Intel Silvermont platform.
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+
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+ Enables -march=silvermont
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+
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+config MGOLDMONT
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+ bool "Intel Goldmont"
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+ select X86_P6_NOP
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+ ---help---
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+
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+ Select this for the Intel Goldmont platform including Apollo Lake and Denverton.
|
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+
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+ Enables -march=goldmont
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+
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+config MGOLDMONTPLUS
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+ bool "Intel Goldmont Plus"
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+ select X86_P6_NOP
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+ ---help---
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+
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+ Select this for the Intel Goldmont Plus platform including Gemini Lake.
|
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+
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+ Enables -march=goldmont-plus
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+
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+config MSANDYBRIDGE
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+ bool "Intel Sandy Bridge"
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+ select X86_P6_NOP
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+ ---help---
|
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+
|
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+ Select this for 2nd Gen Core processors in the Sandy Bridge family.
|
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+
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+ Enables -march=sandybridge
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+
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+config MIVYBRIDGE
|
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+ bool "Intel Ivy Bridge"
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+ select X86_P6_NOP
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+ ---help---
|
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+
|
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+ Select this for 3rd Gen Core processors in the Ivy Bridge family.
|
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+
|
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+ Enables -march=ivybridge
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+
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+config MHASWELL
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+ bool "Intel Haswell"
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+ select X86_P6_NOP
|
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+ ---help---
|
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+
|
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+ Select this for 4th Gen Core processors in the Haswell family.
|
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+
|
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+ Enables -march=haswell
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+
|
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+config MBROADWELL
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+ bool "Intel Broadwell"
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+ select X86_P6_NOP
|
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+ ---help---
|
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+
|
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+ Select this for 5th Gen Core processors in the Broadwell family.
|
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+
|
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+ Enables -march=broadwell
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+
|
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+config MSKYLAKE
|
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+ bool "Intel Skylake"
|
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+ select X86_P6_NOP
|
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+ ---help---
|
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+
|
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+ Select this for 6th Gen Core processors in the Skylake family.
|
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+
|
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+ Enables -march=skylake
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+
|
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+config MSKYLAKEX
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+ bool "Intel Skylake X"
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+ select X86_P6_NOP
|
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+ ---help---
|
||||
+
|
||||
+ Select this for 6th Gen Core processors in the Skylake X family.
|
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+
|
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+ Enables -march=skylake-avx512
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+
|
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+config MCANNONLAKE
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+ bool "Intel Cannon Lake"
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+ select X86_P6_NOP
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+ ---help---
|
||||
+
|
||||
+ Select this for 8th Gen Core processors
|
||||
+
|
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+ Enables -march=cannonlake
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+
|
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+config MICELAKE
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+ bool "Intel Ice Lake"
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+ select X86_P6_NOP
|
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+ ---help---
|
||||
+
|
||||
+ Select this for 10th Gen Core processors in the Ice Lake family.
|
||||
+
|
||||
+ Enables -march=icelake-client
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+
|
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+config MCASCADELAKE
|
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+ bool "Intel Cascade Lake"
|
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+ select X86_P6_NOP
|
||||
+ ---help---
|
||||
+
|
||||
+ Select this for Xeon processors in the Cascade Lake family.
|
||||
+
|
||||
+ Enables -march=cascadelake
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||||
+
|
||||
+config MCOOPERLAKE
|
||||
+ bool "Intel Cooper Lake"
|
||||
+ select X86_P6_NOP
|
||||
+ ---help---
|
||||
+
|
||||
+ Select this for Xeon processors in the Cooper Lake family.
|
||||
+
|
||||
+ Enables -march=cooperlake
|
||||
+
|
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+config MTIGERLAKE
|
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+ bool "Intel Tiger Lake"
|
||||
+ select X86_P6_NOP
|
||||
+ ---help---
|
||||
+
|
||||
+ Select this for third-generation 10 nm process processors in the Tiger Lake family.
|
||||
+
|
||||
+ Enables -march=tigerlake
|
||||
|
||||
config GENERIC_CPU
|
||||
bool "Generic-x86-64"
|
||||
@@ -287,6 +514,19 @@ config GENERIC_CPU
|
||||
Generic x86-64 CPU.
|
||||
Run equally well on all x86-64 CPUs.
|
||||
|
||||
+config MNATIVE
|
||||
+ bool "Native optimizations autodetected by GCC"
|
||||
+ ---help---
|
||||
+
|
||||
+ GCC 4.2 and above support -march=native, which automatically detects
|
||||
+ the optimum settings to use based on your processor. -march=native
|
||||
+ also detects and applies additional settings beyond -march specific
|
||||
+ to your CPU, (eg. -msse4). Unless you have a specific reason not to
|
||||
+ (e.g. distcc cross-compiling), you should probably be using
|
||||
+ -march=native rather than anything listed below.
|
||||
+
|
||||
+ Enables -march=native
|
||||
+
|
||||
endchoice
|
||||
|
||||
config X86_GENERIC
|
||||
@@ -311,7 +551,7 @@ config X86_INTERNODE_CACHE_SHIFT
|
||||
config X86_L1_CACHE_SHIFT
|
||||
int
|
||||
default "7" if MPENTIUM4 || MPSC
|
||||
- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
|
||||
+ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
|
||||
default "4" if MELAN || M486SX || M486 || MGEODEGX1
|
||||
default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
|
||||
|
||||
@@ -329,35 +569,36 @@ config X86_ALIGNMENT_16
|
||||
|
||||
config X86_INTEL_USERCOPY
|
||||
def_bool y
|
||||
- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
|
||||
+ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE
|
||||
|
||||
config X86_USE_PPRO_CHECKSUM
|
||||
def_bool y
|
||||
- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
|
||||
+ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MATOM || MNATIVE
|
||||
|
||||
config X86_USE_3DNOW
|
||||
def_bool y
|
||||
depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
|
||||
|
||||
-#
|
||||
-# P6_NOPs are a relatively minor optimization that require a family >=
|
||||
-# 6 processor, except that it is broken on certain VIA chips.
|
||||
-# Furthermore, AMD chips prefer a totally different sequence of NOPs
|
||||
-# (which work on all CPUs). In addition, it looks like Virtual PC
|
||||
-# does not understand them.
|
||||
-#
|
||||
-# As a result, disallow these if we're not compiling for X86_64 (these
|
||||
-# NOPs do work on all x86-64 capable chips); the list of processors in
|
||||
-# the right-hand clause are the cores that benefit from this optimization.
|
||||
-#
|
||||
config X86_P6_NOP
|
||||
- def_bool y
|
||||
- depends on X86_64
|
||||
- depends on (MCORE2 || MPENTIUM4 || MPSC)
|
||||
+ default n
|
||||
+ bool "Support for P6_NOPs on Intel chips"
|
||||
+ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE)
|
||||
+ ---help---
|
||||
+ P6_NOPs are a relatively minor optimization that require a family >=
|
||||
+ 6 processor, except that it is broken on certain VIA chips.
|
||||
+ Furthermore, AMD chips prefer a totally different sequence of NOPs
|
||||
+ (which work on all CPUs). In addition, it looks like Virtual PC
|
||||
+ does not understand them.
|
||||
+
|
||||
+ As a result, disallow these if we're not compiling for X86_64 (these
|
||||
+ NOPs do work on all x86-64 capable chips); the list of processors in
|
||||
+ the right-hand clause are the cores that benefit from this optimization.
|
||||
+
|
||||
+ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
|
||||
|
||||
config X86_TSC
|
||||
def_bool y
|
||||
- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
|
||||
+ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE || MATOM) || X86_64
|
||||
|
||||
config X86_CMPXCHG64
|
||||
def_bool y
|
||||
@@ -367,7 +608,7 @@ config X86_CMPXCHG64
|
||||
# generates cmov.
|
||||
config X86_CMOV
|
||||
def_bool y
|
||||
- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
|
||||
+ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
|
||||
|
||||
config X86_MINIMUM_CPU_FAMILY
|
||||
int
|
||||
--- a/arch/x86/Makefile 2020-05-14 01:58:30.000000000 -0400
|
||||
+++ b/arch/x86/Makefile 2020-05-16 10:10:41.903122145 -0400
|
||||
@@ -119,13 +119,57 @@ else
|
||||
KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
|
||||
|
||||
# FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
|
||||
+ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
|
||||
cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
|
||||
+ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8)
|
||||
+ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
|
||||
+ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
|
||||
+ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
|
||||
+ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
|
||||
+ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
|
||||
+ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
|
||||
+ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
|
||||
+ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
|
||||
+ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
|
||||
+ cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2)
|
||||
cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
|
||||
|
||||
cflags-$(CONFIG_MCORE2) += \
|
||||
- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
|
||||
- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
|
||||
- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
|
||||
+ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
|
||||
+ cflags-$(CONFIG_MNEHALEM) += \
|
||||
+ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
|
||||
+ cflags-$(CONFIG_MWESTMERE) += \
|
||||
+ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
|
||||
+ cflags-$(CONFIG_MSILVERMONT) += \
|
||||
+ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
|
||||
+ cflags-$(CONFIG_MGOLDMONT) += \
|
||||
+ $(call cc-option,-march=goldmont,$(call cc-option,-mtune=goldmont))
|
||||
+ cflags-$(CONFIG_MGOLDMONTPLUS) += \
|
||||
+ $(call cc-option,-march=goldmont-plus,$(call cc-option,-mtune=goldmont-plus))
|
||||
+ cflags-$(CONFIG_MSANDYBRIDGE) += \
|
||||
+ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
|
||||
+ cflags-$(CONFIG_MIVYBRIDGE) += \
|
||||
+ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
|
||||
+ cflags-$(CONFIG_MHASWELL) += \
|
||||
+ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
|
||||
+ cflags-$(CONFIG_MBROADWELL) += \
|
||||
+ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
|
||||
+ cflags-$(CONFIG_MSKYLAKE) += \
|
||||
+ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
|
||||
+ cflags-$(CONFIG_MSKYLAKEX) += \
|
||||
+ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
|
||||
+ cflags-$(CONFIG_MCANNONLAKE) += \
|
||||
+ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake))
|
||||
+ cflags-$(CONFIG_MICELAKE) += \
|
||||
+ $(call cc-option,-march=icelake-client,$(call cc-option,-mtune=icelake-client))
|
||||
+ cflags-$(CONFIG_MCASCADELAKE) += \
|
||||
+ $(call cc-option,-march=cascadelake,$(call cc-option,-mtune=cascadelake))
|
||||
+ cflags-$(CONFIG_MCOOPERLAKE) += \
|
||||
+ $(call cc-option,-march=cooperlake,$(call cc-option,-mtune=cooperlake))
|
||||
+ cflags-$(CONFIG_MTIGERLAKE) += \
|
||||
+ $(call cc-option,-march=tigerlake,$(call cc-option,-mtune=tigerlake))
|
||||
+ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \
|
||||
+ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
|
||||
cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
|
||||
KBUILD_CFLAGS += $(cflags-y)
|
||||
|
||||
--- a/arch/x86/Makefile_32.cpu 2020-05-14 01:58:30.000000000 -0400
|
||||
+++ b/arch/x86/Makefile_32.cpu 2020-05-16 10:10:41.903122145 -0400
|
||||
@@ -23,7 +23,19 @@ cflags-$(CONFIG_MK6) += -march=k6
|
||||
# Please note, that patches that add -march=athlon-xp and friends are pointless.
|
||||
# They make zero difference whatsosever to performance at this time.
|
||||
cflags-$(CONFIG_MK7) += -march=athlon
|
||||
+cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
|
||||
cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
|
||||
+cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon)
|
||||
+cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon)
|
||||
+cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon)
|
||||
+cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon)
|
||||
+cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon)
|
||||
+cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon)
|
||||
+cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon)
|
||||
+cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon)
|
||||
+cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon)
|
||||
+cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon)
|
||||
+cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2,-march=athlon)
|
||||
cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
|
||||
cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
|
||||
cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
|
||||
@@ -32,8 +44,24 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc-
|
||||
cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
|
||||
cflags-$(CONFIG_MVIAC7) += -march=i686
|
||||
cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
|
||||
-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
|
||||
- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
|
||||
+cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem)
|
||||
+cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere)
|
||||
+cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont)
|
||||
+cflags-$(CONFIG_MGOLDMONT) += -march=i686 $(call tune,goldmont)
|
||||
+cflags-$(CONFIG_MGOLDMONTPLUS) += -march=i686 $(call tune,goldmont-plus)
|
||||
+cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge)
|
||||
+cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge)
|
||||
+cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell)
|
||||
+cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell)
|
||||
+cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake)
|
||||
+cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512)
|
||||
+cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake)
|
||||
+cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake-client)
|
||||
+cflags-$(CONFIG_MCASCADELAKE) += -march=i686 $(call tune,cascadelake)
|
||||
+cflags-$(CONFIG_MCOOPERLAKE) += -march=i686 $(call tune,cooperlake)
|
||||
+cflags-$(CONFIG_MTIGERLAKE) += -march=i686 $(call tune,tigerlake)
|
||||
+cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \
|
||||
+ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
|
||||
|
||||
# AMD Elan support
|
||||
cflags-$(CONFIG_MELAN) += -march=i486
|
||||
|
||||
Loading…
Reference in a new issue